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| OKI Semiconductor MSM5412222B 262,214-Word x 12-Bit Field Memory FEDS5412222B-01 Issue Date: Nov.,20, 2002 GENERAL DESCRIPTION The OKI MSM5412222B is a high performance 3-Mbit, 256K x 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222B is a FRAM for wide or low end use in general commodity TVs and VTRs exclusively. MSM5412222B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. More than two MSM5412222Bs can be cascaded directly without any delay devices among the MSM5412222Bs. (Cascading of MSM5412222B provides larger storage depth or a longer delay). Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams. The MSM5412222B provides high speed FIFO, First-In First-Out, operation without external refreshing: MSM5412222B refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM5412222B's function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 x 12-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. Additionally, the MSM5412222B has write mask function or input enable function (IE), and read-data skipping function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MSM5412222B. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture" on a TV screen. The MSM5412222B is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514222C and 2-Mbit Field Memory MSM518222A. Three MSM514222Cs or one MSM514222C plus one MSM518222A can be replaced simply by one MSM5412222B. 1/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B FEATURES * * * * * * * * * Single power supply: 5.0 V 0.5 V 262,214 words x 12 bits Fast FIFO (First-In First-Out) operation High speed asynchronous serial access Read/write cycle time 25 ns/30 ns Access time 23 ns/25 ns Direct cascading capability Write mask function (Input enable control) Data skipping function (Output enable control) Self refresh (No refresh control is required) Package options: 44-pin 400 mil plastic TSOP (Type 2) (TSOP(2)44-P-400-0.80-K) (Product:MSM5412222B-XXTS-K) 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product: MSM5412222B-xxJS) xx indicates speed rank. PRODUCT FAMILY Family MSM5412222B-25TS-K MSM5412222B-30TS-K MSM5412222B-25JS MSM5412222B-30JS Access Time (Max.) 23 ns 25 ns 23 ns 25 ns Cycle Time (Min.) 25 ns 30 ns 25 ns 30 ns Package 400 mil 44-pin TSOP (2) 400 mil 40-pin SOJ 2/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B PIN CONFIGURATION (TOP VIEW) VSS DIN11 DIN10 NC DIN9 DIN8 DIN7 DIN6 NC DIN5 DIN4 DIN3 DIN2 NC DIN1 DIN0 SWCK RSTW NC WE IE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DOUT11 DOUT10 NC DOUT9 DOUT8 DOUT7 DOUT6 VCC DOUT5 DOUT4 DOUT3 DOUT2 VSS DOUT1 DOUT0 SRCK RSTR NC RE OE VCC VSS 1 NC 2 DIN11 3 DIN10 4 DIN9 5 40 VSS 39 VCC 38 DOUT11 37 DOUT10 36 DOUT9 35 DOUT8 34 DOUT7 33 DOUT6 32 DOUT5 31 DOUT4 30 DOUT3 29 DOUT2 28 DOUT1 27 DOUT0 26 SRCK 25 RSTR 24 RE 23 OE 22 VSS 21 VCC DIN8 6 DIN7 7 DIN6 8 DIN5 9 DIN4 10 DIN3 11 DIN2 12 DIN1 13 DIN0 14 SWCK 15 RSTW 16 WE 17 IE 18 NC 19 VCC 20 44-Pin Plastic TSOP (2) (K Type) 40-Pin Plastic SOJ Pin Name SWCK SRCK WE RE IE OE RSTW RSTR DIN0 to 11 DOUT0 to 11 VCC VSS NC Function Serial Write Clock Serial Read Clock Write Enable Read Enable Input Enable Output Enable Write Reset Clock Read Reset Clock Data Input Data Output Power Supply (5.0 V) Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 3/17 DOUT ( x 12) OE RE RSTR SRCK OKI Semiconductor BLOCK DIAGRAM Data-Out Buffer ( x 12) Serial Read Controller Serial Read Register ( x 12) Read Line Buffer ( x 12) 71-Word Sub-Register ( x 12) 262,144 x 12 Memory Array 71-Word Sub-Register ( x 12) ( x 12) Write Line Buffer Serial Write Register ( x 12) VBB Generator Serial Write Controller Clock Oscillator X Decoder Read/Write and Refresh Controller Data-In Buffer ( x 12) FEDS5412222B-01 MSM5412222B DIN ( x 12) IE WE RSTW SWCK 4/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 150 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM5412222B is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset: RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs: DIN0 to 11 Write Clock: SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable: WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM5412222B is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK. 5/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B Read Operation The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 150 active read cycles, i.e. SRCK cycles while RE is high. Read Reset: RSTR The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Data Out: DOUT0 to 11 Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MSM5412222B. Read Enable: RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable: OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK. 6/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 s after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 s stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 20 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 20 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, the delay between an RSTW operation and an RSTR operation must be at least 150 SRCK cycles. If the delay between RSTW and RSTR operations is more than 21 but less than 150 cycles, then the data read out will be undetermined. It may be "old data" or "new" data, or a combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM5412222B is designed to allow easy cascading of multiple memory devices. This provides higher storage depth, or a longer delay than can be achieved with only one memory device. 7/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Conditon at Ta = 25C, VSS Ta = 25C Ta = 25C -- -- Rating -1.0 to +7.0 50 1 0 to 70 -55 to +150 Unit V mA W C C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 4.5 2.4 -0.1 Typ 5.0 VCC 0 Max. 5.5 VCC +1 +0.8 Unit V V V DC Characteristics Parameter Input Leakage Current Output Leakage Current Output "H" Level Voltage Output "L" Level Voltage Operating Current Standby Current Symbol ILI ILO VOH VOL ICC1 ICC2 Condition 0 < VI < VCC + 1 V, Other Pins Tested at V = 0 V 0 < VO < VCC IOH = -1 mA IOL = 2 mA Minimum Cycle Time, Output Open Input Pin = VIH/VIL Min. -10 -10 2.4 -- -- -- Max. +10 +10 -- 0.4 60 5 Unit A A V V mA mA Capacitance (Ta = 25C, f = 1 MHz) Parameter Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) Output Capacitance (DOUT) Symbol CI CO Max. 6 7 Unit pF pF 8/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B AC Characteristics (VCC = 5.0 V 0.5 V, Ta = 0 to 70C) Parameter Access Time from SRCK DOUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Data Setup Time Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable SetupTime RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable SetupTime OE Disable Hold Time Output Buffer Turn-off Delay Time from OE RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) Symbol tAC tDDCK tDECK tWSWH tWSWL tDS tDH tWENS tWENH tWDSS tWDSH tIENS tIENH tIDSS tIDSH tWWEH tWWEL tWIEH tWIEL tRSTWS tRSTWH tWSRH tWSRL tRENS tRENH tRDSS tRDSH tOENS tOENH tODSS tODSH tOEZ tWREH tWREL tWOEH tWOEL tRSTRS tRSTRH tSWC tSRC tT MSM5412222B-25 Min. -- 6 6 9 10 2 4 0 3 0 3 0 3 0 3 5 5 5 5 0 3 9 10 0 3 0 3 0 3 0 3 17 5 5 5 5 0 3 25 25 3 Max. 23 -- 23 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 MSM5412222B-30 Min. -- 6 6 12 12 2 4 0 3 0 3 0 3 0 3 10 10 10 10 0 3 12 12 0 3 0 3 0 3 0 3 17 10 10 10 10 0 3 30 30 3 Max. 25 -- 25 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 150 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 150 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 20 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 21 and less than 149, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH = 2.0 V and VOL = 0.8 V. 10/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B TIMING WAVEFORM Write Cycle Timing (Write Reset) n cycle SWCK tT RSTW tDS DIN tDH n-1 n 0 1 2 tRSTWS tRSTWH tWSWH tWSWL 0 cycle 1 cycle 2 cycle -VIH -VIL tSWC -VIH -VIL -VIH -VIL WE -VIH -VIL IE -VIH -VIL Write Cycle Timing (Write Enable) n cycle SWCK tWENH WE tWWEL DIN n-1 n tWWEH n+1 -VIH -VIL tWDSH tWDSS tWENS -VIH -VIL Disable cycle Disable cycle n + 1 cycle -VIH -VIL IE -VIH -VIL RSTW -VIH -VIL 11/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B Write Cycle Timing (Input Enable) n cycle SWCK tIENH IE tWIEL DIN n-1 n tWIEH n+3 -VIH -VIL tIDSH tIDSS tIENS -VIH -VIL n + 1 cycle n + 2 cycle n + 3 cycle -VIH -VIL WE -VIH -VIL -VIH -VIL RSTW Read Cycle Timing (Read Reset) n cycle SRCK tRSTRS tRSTRH tWSRH tWSRL -VIH -VIL -VOH -VOL -VIH -VIL -VIH -VIL 0 cycle 1 cycle 2 cycle -VIH -VIL tT RSTR tAC DOUT n-1 n 0 tDDCK 1 2 tSRC RE OE 12/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B Read Cycle Timing (Read Enable) n cycle SRCK tRENH RE tWREL DOUT n-1 tWREH n n+1 tRDSH tRDSS tRENS -VIH -VIL Disable cycle Disable cycle n + 1 cycle -VIH -VIL -VOH -VOL OE -VIH -VIL -VIH -VIL RSTR Read Cycle Timing (Output Enable) n cycle SRCK tOENH OE tWOEL DOUT n-1 n tOEZ tWOEH Hi-Z tDECK n+3 -VOH -VOL tODSH tODSS tOENS -VIH -VIL n + 1 cycle n + 2 cycle n + 3 cycle -VIH -VIL RE -VIH -VIL -VIH -VIL RSTR 13/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B PACKAGE DIMENSIONS (Unit: mm) TSOP(2)44-P-400-0.80-K Mirror finish 5 Notes for Mounting the Surface Mount Type Packages Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.54 TYP. 3/Dec. 10, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B (Unit: mm) SOJ40-P-400-1.27 Mirror finish 5 Notes for Mounting the Surface Mount Type Packages Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 1.70 TYP. 5/Dec. 5, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B REVISION HISTORY Document No. FEDS5412222B-01 Date Nov.,20 , 2002 Page Previous Current Edition Edition - - Final edition 1 Description 16/17 FEDS5412222B-01 OKI Semiconductor MSM5412222B NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 17/17 |
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